Xilinx Field Programmable Gate Array - FPGA - part # XC2C384-7TQG144C A9B10017152 • LUT/dual flip-flop pair for

• LUT/dual flip-flop pair for applications requiring rich

and mask signals • Programmable CAS (READ) latency (CL) • Programmable posted CAS additive latency (AL) • Programmable CAS (WRITE) latency (CWL) • Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS]) • Selectable BC4 or BL8 on-the-fly (OTF) • Self refresh mode • Refresh maximum interval time at TC temperature range – 64ms at –40°C to +85°C – 32ms at +85°C to +105°C – 16ms at +105°C to +115°C – 8ms at +115°C to +125°C • Self refresh temperature (SRT) • Automatic self refresh (ASR) • Write leveling • Multipurpose register • Output driver calibration • AEC-Q100 • PPAP submission • 8D response time

BRM:SS06-0B00-00

each channel includes a latch to turn off that channel if the maximum channel current is exceeded

• 16-bit or 32-bit interfaces to DDR3

Xilinx Field Programmable Gate Array - FPGA - part # XC2C384-7TQG144C A9B10017152 • LUT/dual flip-flop pair forThe Xilinx XC2C384 7TQG144C Spartan II Field Programmable Gate Array family gives users high performance, abundant logic resources, and a rich feature set, all at an exceptionally low price. The six member family offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I O standards, and four DLLs. Fast,